Semiconductor device having multi-layered wiring

ABSTRACT

A semiconductor device is provided with a first insulating film, a first wiring layer formed in the first insulating film, a second insulating film formed above the first wiring layer and the first insulating film, the second insulating film including a low dielectric constant film, a second wiring layer formed in the second insulating film and coupled to the first wiring layer through a first connection section, and a third insulating film formed above the second wiring layer and the second insulating film and serving as one of an interlayer insulating film and a passivation film, and at least one of the first and third insulating films being one of a film formed mainly of SiON, a film formed mainly of SiN, and a laminated film being the films formed mainly of SiON or SiN respectively.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2001-157195, filed May 25,2001, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having amulti-layered wiring structure.

2. Description of the Related Art

In recent semiconductor technology, an interlayer insulating film mustbe made of a low dielectric constant film. In general, the lowdielectric constant film has a low film density and is permeable towater. Even if a very small amount of water, which has a relativedielectric constant k as large as 80 (a maximum value), is contained inthe low dielectric constant film, the dielectric constant of the lowdielectric constant film inevitably increases. In order to ensureeffective use of the low dielectric constant film, therefore, it isnecessary to prevent water or moisture from entering the low dielectricconstant film.

FIG. 12 is a plan view showing a semiconductor device according to thefirst example of the prior art, and FIG. 13 is a sectional view takenalong line XIII—XIII in FIG. 12.

As shown in FIGS. 12 and 13, a gate electrode 72 is formed on asemiconductor substrate 71. A BPSG (Boron Phosphorous Silicate Glass)film 73 is formed in such a manner as to cover the gate electrode 72. Acontact plug 75 is formed inside the BPSG film 73. A first wiring layer74 is formed on the BPSG film 73 in such a manner that the first wiringlayer 74 is connected to the contact plug 75. A TEOS (Tetra Ethyl OrthoSilicate)-SiO₂ film 76 is formed in such a manner as to cover the firstwiring layer 74, and this TEOS-SiO₂ is overlaid with a second wiringlayer 77. The second wiring layer 77 is connected to the first wiringlayer 74 by way of a via 78. A passivation film 84, which is made up ofa PSG film 79 and an SiN film 80, is formed in such a manner as to coverthe second wiring layer 77. A via ring 81, which is made by the firstand second wiring layers 74 and 77, the contact plug 75 and the via 78,is formed along the periphery of a chip 70. The via ring 81 is intendedto prevent cracks at the time of scribing.

In the structure of the first example of the prior art, the passivationfilm 84 is not a single-layer film. It is a laminated film made up ofthe PSG film 79 (or another type of SiO₂ film) and the SiN film 80formed on the PSG film 79. This laminated structure serves to suppressthe total stress of the film. The structure of the first example of theprior art raises a problem if an opening is formed in the passivationfilm 84 to provide a pad window. If such an opening is formed, the PSGfilm 79 is exposed in the wall surface of the opening. Since the exposedportion of the PSG film 79 undesirably serves as an inlet of moisture,it is hard to prevent the water or moisture from entering the chip.

In the process of forming the contact plug 75 and the wiring layers 74and 77 by use of an Al material, the via ring 81 serves to prevent waterfrom entering the chip from the side portions of the chip. Thisadvantage cannot be expected if the contact plug 75 is formed of W.

FIG. 14 is a plan view showing a semiconductor device according to thesecond example of the prior art. FIG. 15A is a sectional view takenalong line XVA—XVA in FIG. 14, and FIG. 15B is a sectional view takenalong line XVB—XVB in FIG. 14.

As can be seen from FIGS. 14 and 15A, in the case where the contact plug82 is formed of W, the contact plug 82 easily separate from thesemiconductor substrate 71. To prevent the contact plug 82 fromseparating from the substrate 71, a plug such as the via ring 81 of FIG.13 is not easy to form. Although columnar contact plugs 82 can be formedinstead as shown in FIG. 15B, gaps 83 are inevitably produced betweenthe contact plugs 82. Since the multi-layered wiring structure cannot becompletely covered, it is hard to prevent water from entering the chip70 from the side portions of the chip.

As described above, the prior art is not effective in completelyprotecting the chip from moisture, which may enter the chip from thetop, bottom or side portions thereof. In other words, the prior art doesnot enable effective utilization of the characteristics of a lowdielectric constant film.

BRIEF SUMMARY OF THE INVENTION

A semiconductor device according to one aspect of the inventioncomprises a first insulating film; a first wiring layer formed in thefirst insulating film; a second insulating film formed above the firstwiring layer and the first insulating film, the second insulating filmincluding a low dielectric constant film; a second wiring layer formedin the second insulating film and coupled to the first wiring layerthrough a first connection section; and a third insulating film formedabove the second wiring layer and the second insulating film and servingas one of an interlayer insulating film and a passivation film, and atleast one of the first and third insulating films being one of a filmformed mainly of SiON, a film formed mainly of SiN, and a laminated filmbeing the films formed mainly of SiON or SiN respectively.

A semiconductor device according to another aspect of the inventioncomprises a first insulating film; a first wiring layer formed above thefirst insulating film; a second insulating film formed above the firstwiring layer and the first insulating film, the second insulating filmincluding a low dielectric constant film; a second wiring layer formedin the second insulating film and coupled to the first wiring layerthrough a first connection section; and a third insulating film formedabove the second wiring layer and the second insulating film and servingas one of an interlayer insulating film and a passivation film, and atleast one of the first and third insulating films being one of a filmformed mainly of SiON, a film formed mainly of SiN, and a laminated filmbeing the films formed mainly of SiON or SiN respectively.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently embodiments of theinvention, and together with the general description given above and thedetailed description of the embodiments given below, serve to explainthe principles of the invention.

FIG. 1 is a plan view showing a semiconductor device according to oneembodiment of the present invention.

FIG. 2 is a sectional view of the semiconductor device, which is takenalong line II—II in FIG. 1.

FIG. 3 illustrates the second embodiment of the present invention and isa sectional view showing a semiconductor device wherein an SiON film isused as an interlayer insulating film located at a high level.

FIG. 4 illustrates the second embodiment of the present invention and isa sectional view showing a semiconductor device wherein a TEOS film isused as an interlayer insulating film located at a high level.

FIG. 5 illustrates the third embodiment of the present invention and isa sectional view showing a semiconductor device wherein an SiON film isused as a low dielectric constant film located at a low level.

FIG. 6 illustrates the third embodiment of the present invention and isa sectional view showing a semiconductor device wherein an SiON film isused as a low dielectric constant film located at a high level.

FIG. 7 is a sectional view showing a semiconductor device which has astructure similar to that shown in FIG. 5 and employs an SiON film as aninterlayer insulating film located at a high level.

FIG. 8 is a sectional view showing a semiconductor device which has astructure similar to that shown in FIG. 6 and employs an SiON film as aninterlayer insulating film located at a high level.

FIG. 9 is a sectional view showing a semiconductor device which has astructure similar to that shown in FIG. 5 and employs a TEOS film as aninterlayer insulating film located at a high level.

FIG. 10 is a sectional view showing a semiconductor device which has astructure similar to that shown in FIG. 6 and employs a TEOS film as aninterlayer insulating film located at a high level.

FIG. 11 is a sectional view showing a semiconductor device according tothe fourth embodiment of the present invention.

FIG. 12 is a plan view showing a semiconductor according to the firstexample of the prior art.

FIG. 13 is a sectional view of the semiconductor device, which is takenalong line XIII—XIII in FIG. 12.

FIG. 14 is a plan view showing a semiconductor according to the secondexample of the prior art.

FIG. 15A is a sectional view of the semiconductor device, which is takenalong line XVA—XVA in FIG. 14.

FIG. 15B is a sectional view of the semiconductor device, which is takenalong line XVB—XVB in FIG. 14.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to a multi-layered wiring structurewherein an interlayer insulating film is made of a low dielectricconstant film whose specific dielectric constant k is not more than 3.The low dielectric constant film is formed of polymethyl siloxane,hydrogen silsesquioxane, an organic material having a low dielectricconstant (e.g. an aromatic hydrocarbon polymer), or the like.

Embodiments of the present invention will now be described withreference to the accompanying drawings. In the descriptions below, thesame reference numerals will be used to denote corresponding or similarstructural elements.

[First Embodiment]

The first embodiment is featured in that a high-level interlayerinsulating film, which is a low dielectric constant film, and the layersbetween the lowermost wiring layers, are made of a film with low waterabsorption and water permeability.

The “film with low water absorption and water permeability” used hereinis a film that lower than a TEOS (Tetra Ethyl Ortho Silicate)-SiO₂ filmand a USG (Undoped Silicate Glass) film. The TEOS-SiO₂ film is aninsulating film formed in the PECVD (Plasma Enhanced Chemical VaporDeposition) process that uses a TEOS gas (which has been used in theconventional semiconductor device manufacture process) as a rawmaterial. The USG film is formed by use of SiH₄ and O₂ gases.

FIG. 1 is a plan view showing a semiconductor according to the firstembodiment of the present invention. FIG. 2 is a sectional view of thesemiconductor device, which is taken along line II—II in FIG. 1.

As shown in FIG. 1, a via ring 30 is formed along the periphery of achip 10. The via ring 30 surrounds the device area of the chip 10.

As shown in FIG. 2, a gate electrode 12 is formed on a semiconductorsubstrate 11. A BPSG (Boron Phosphorous Silicate Glass) film 13 isformed in such a manner as to cover the gate electrode 12, and aTEOS-SiO₂ film 14 is formed on the BPSG film 13. A contact plug 15,which is made of W, is formed in the TEOS-SiO₂ film 14 and BPSG film 13.An SiON film 16, which has a thickness of 150 nm, for example, is formedon the TEOS-SiO₂ film 14. A first wiring layer 17, made of Cu or Al, isformed inside the SiON film 16. The first wiring layer 17 is connectedto the contact plug 15.

The first wiring layer 17 and the SiON film 16 are overlaid with adiffusion preventing film 18 having a thickness of 70 nm, for example.This diffusion preventing film 18 is formed of any one of SiN, SiC, SiOCand SiCN. The diffusion preventing film 18 is overlaid with a first lowdielectric constant film 19. A second wiring layer 20, made of Cu or Al,is formed inside the first low dielectric constant film 19, and isconnected to the first wiring layer 17 through a first via 21. Adiffusion preventing film 22 having a thickness of 70 nm, for example,and formed of any one of SiN, SiC, SiOC and SiCN is formed on both thesecond wiring layer 20 and the first low dielectric constant film 19.The diffusion preventing film 22 is overlaid with a second lowdielectric constant film 23. A third wiring layer 24, made of Cu or Al,is formed inside the second low dielectric constant film 23, and isconnected to the second wiring layer 20 through a second via 25. Adiffusion preventing film 26 having a thickness of 70 nm, for example,and formed of any one of SiN, SiC, SiOC and SiCN is formed on both thethird wiring layer 24 and the second low dielectric constant film 23.The diffusion preventing film 26 is overlaid with a third low dielectricconstant film 27. A fourth wiring layer 28, made of Cu or Al, is formedinside the third low dielectric constant film 27, and is connected tothe third wiring layer 24 through a third via 29. In this manner, thevia ring 30 formed along the periphery of the chip 10 has a continuousgroove defined by the vias 21, 25 and 29 and wiring layers 17, 20, 24,28.

A diffusion preventing film 31 having a thickness of 70 nm, for example,and formed of any one of SiN, SiC, SiOC and SiCN is formed on both thefourth wiring layer 28 and the third low dielectric constant film 27. AnSiON film 32 having a thickness of 150 nm, for example, is formed on thediffusion preventing film 31. The SiON film 32 is then overlaid with anSiN film 33 having a thickness of 400 nm, for example. The SiON film 32and the SiN film 33 serve as a passivation film 34. The diffusionpreventing film 31, the SiON film 32 and the SiN film 33 are selectivelyremoved to form a pad window 35. The fourth wiring layer 28, the surfaceof which is exposed by the formation of the pad window 35, serves as apad electrode 36.

In the multi-layered semiconductor device provided with low dielectricconstant films 19, 23 and 27, the passivation film 34 is located in theuppermost layer of the chip 10, and the via ring 30 formed around thechip 10 and located in the neighborhood of the passivation film 34. Inaddition, the SiON film 16 adjacent to the via ring 30 is locatedbetween the first wiring layers 17. Furthermore, the passivation film 34includes the SiON film 32.

Each of the SiON films 16 and 32 may be replaced with an SiN film or alaminated film made up of an SiON film and an SiN film. The SiON and theSiN films can be formed, for example, in the method described below.

The SiON film is formed in the PECVD process, using (SiH₄+N₂O),(SiH₄+N₂O+N₂), (SiH₄+O₂+N₂) or (SiH₄+O₂+NH₃) as a raw material gas. TheSiON film can be formed, using another kind of raw material gas, as longas the raw material gas contains Si, O or N.

Likewise, the SiN film is formed in the PECVD process, using (SiH₄+N₂)or (SiH₄+NH₃) as a raw material gas. The SiN film can be formed, usinganother kind of raw material gas, as long as the raw material gascontains Si or N.

The SiON film and the SiN film may contain hydrogen components.

The SiON films 16 and 32 desirably have a thickness of not less than 100nm, since the SiON films 16 and 32 having such thickness are effectivein preventing moisture from entering the interior.

In many cases, the first wiring layer 17 is used as a local wiring layer(i.e., a wiring layer used for connection within a cell). Even if theregion between the first wiring layers has only a high capacitance, thisdoes not significantly affect the performance of the device. For thisreason, a film having a remarkable water blocking effect, like an SiONfilm, can be provided in the region between the first wing layers.

The first embodiment described above employs a SiON film 32 of apassivation film 34 located in the uppermost layer of the chip 10, and avia ring 30 located on the side of the chip 10. In addition to these,the first embodiment employs an SiON film 16 in the region between thefirst wiring layers. With this structure, all routes through whichmoisture may enter the chip 10 can be blocked; in other words, moistureentry from above the chip, moisture entry from below the chip, andmoisture entry from the side portions of the chip are prevented. Hence,the low dielectric constant films are protected from moisture, and theirdielectric constants do not undesirably increase. Accordingly, the firstembodiment can provide a semiconductor device that makes good use of thecharacteristics of the low dielectric constant films.

The SiON film and the SiN films 16 and 32 can be easily obtained sincethe materials of these films have been used in conventionalsemiconductor processes.

In the structure shown in FIG. 2, the pad window 35 may be filled withAl, thereby forming a pad. In this case as well, the adoption of thepresent invention is effective in preventing moisture from entering theinterior of the chip 10.

[Second Embodiment]

The second embodiment is featured in that a high-level interlayerinsulating film is made of a film with low water absorption and waterpermeability.

FIG. 3 is a sectional view showing a semiconductor device according tothe second embodiment of the present invention. As shown in FIG. 3, thesemiconductor device of the second embodiment is similar to that of thefirst embodiment in that it comprises: a passivation film 34 formed inthe uppermost layer of the chip 10; a via ring 30 formed along theperiphery of the chip 10 and located close to the passivation film 34;and an SiON film 16 formed between the first wiring layers 17 andlocated adjacent to the via ring 30. In addition, the passivation film34 is partly made of an SiON film 32.

The semiconductor device of the second embodiment differs from that ofthe first embodiment in light of the structure of high-level wiringlayers. To be more specific, the upper two wiring layers 45 and 46 areused mainly as a power supply line and a grounding line. For thisreason, the upper two interlayer insulating films 41a and 42a are notlow dielectric constant films but films with low water absorption andwater permeability. Specifically, they are films formed mainly of SiON,films formed mainly of SiN, or laminated films including these. In thismanner, according to the second embodiment, the interlayer insulatingfilms 19 and 23 made of a low dielectric constant film, are surroundedby the following: a passivation film 34; high-level interlayerinsulating films 41a and 42a; a via ring 30 which is defined bycontinuous groove-like vias 21, 25, 29 and 44 and wiring layers 17, 20,24, 28 and 43; and an interlayer insulating film 16 located between thefirst wiring layers 17.

With the second embodiment, it is possible to obtain advantages whichare similar to those of the first embodiment.

Moreover, three films 41a, 42a and 32 with low water absorption andwater permeability are formed above the low dielectric constant films 19and 23. This structure is effective in preventing moisture from enteringthe interior of the chip 10 from above.

As shown in FIG. 4, the upper two interlayer insulating films 41b and42b may be SiO films, such as TEOS films formed in the PECVD process orUSG films.

[Third Embodiment]

The third embodiment is featured in that at least one of high-andlow-level interlayer insulating films made of low dielectric constantfilms, is made of a film with low water absorption and waterpermeability.

FIGS. 5 and 6 are sectional views of a semiconductor device according tothe third embodiment of the present invention. As shown in theseFigures, the semiconductor device of the third embodiment is similar tothat of the first embodiment in that it comprises: a passivation film 34formed in the uppermost layer of the chip 10; and a via ring 30 formedalong the periphery of the chip 10 and located close to the passivationfilm 34. The semiconductor device of the third embodiment differs fromthat of the first embodiment in that either the interlayer insulatingfilm located between the first wiring layers 17 or part of thepassivation film 34 is made of a film with low water absorption andwater permeability. More specifically, either the interlayer insulatingfilm or part of the passivation film is a film formed mainly of SiON, afilm formed mainly of SiN, or a laminated film including these.

In the structure shown in FIG. 5, the interlayer insulating film locatedbetween the first wiring layers 17 is made of an SiON film 16, and partof the passivation film 34 is made of a TEOS film 51. On the other hand,in the structure shown in FIG. 6, the interlayer insulating film locatedbetween the first wiring layers 17 is made of a TEOS film 52, and partof the passivation film 34 is made of an SiON film 32.

The third embodiment described above employs a via ring 30 located onthe side of the chip 10, and an SiON film 32 formed in the uppermostlayer of the chip 10 (alternatively, an SiON film 16 located between thefirst wiring layers 17). With this structure, moisture entry from abovethe chip, moisture entry from below the chip, and moisture entry fromthe side portions of the chip are prevented. Hence, the low dielectricconstant films are protected from moisture, and their dielectricconstants do not undesirably increase. Accordingly, the third embodimentcan provide a semiconductor device that makes good use of thecharacteristics of the low dielectric constant films.

Like the second embodiment, the third embodiment is applicable to thecase where the upper two wiring layers 45 and 46 are used as a powersupply line and a grounding line.

As shown in FIGS. 7 and 8, either the interlayer insulating film locatedbetween the first wiring layers 17 or part of the passivation film 34may be made of a film with low water absorption and water permeability.More specifically, either the interlayer insulating film or part of thepassivation film may be a film formed mainly of SiON, a film formedmainly of SiN, or a laminated film including these. In addition, theupper two interlayer insulating films 41a and 42a may be SiON films.

With this structure shown in FIG. 7, all routes through which moisturemay enter the chip 10 can be blocked. That is, moisture entry from abovethe chip 10, moisture entry from below the chip 10, and moisture entryfrom the side portions of the chip 10 are prevented. The structure shownin FIG. 8 is particularly effective in preventing moisture from enteringthe chip 10 from above.

As shown in FIGS. 9 and 10, either the interlayer insulating filmlocated between the first wiring layers 17 or part of the passivationfilm 34 may be made of a film with low water absorption and waterpermeability. More specifically, either the interlayer insulating filmor part of the passivation film may be a film formed mainly of SiON, afilm formed mainly of SiN, or a laminated film including these. Inaddition, the upper two interlayer insulating films 41a and 42a may beSiO films, such as TEOS films formed in the PECVD process or USG films.

The structure shown in FIG. 9 employs three thick TEOS films 41b, 42band 51, a via ring 30 and an SiON film 16. Hence, all routes throughwhich moisture may enter the chip 10 can be blocked. That is, moistureentry from above the chip 10, moisture entry from below the chip 10, andmoisture entry from the side portions of the chip 10 are prevented. Onthe other hand, the structure shown in FIG. 10 employs TEOS films 41band 42b and an SiON film 32 which are located above the low dielectricconstant films 19 and 23. This structure is particularly effective inpreventing moisture from entering the chip 10 from above.

[Fourth Embodiment]

The fourth embodiment is featured in that a high-level interlayerinsulating film made of a low dielectric constant film and the filmlower in level than the lowermost wiring layer, are films with low waterabsorption and water permeability.

FIG. 11 is a sectional view of a semiconductor device according to thefourth embodiment of the present invention. As shown in FIG. 11, thesemiconductor device of the fourth embodiment is similar to that of thefirst embodiment in that it comprises: a passivation film 34 formed inthe uppermost layer of the chip 10; and a via ring 30 formed along theperiphery of the chip 10 and located close to the passivation film 34.In addition, part of the passivation film 34 is made of an SiON film 32.

The semiconductor device of the fourth embodiment differs from that ofthe first embodiment in that the first wiring layer 17 is formed on anSiON film 61 having a thickness of 150 nm, for example. In other words,according to the fourth embodiment, the passivation film 34, the viaring 30 and the SiON film 61 (on which the first wiring layer 17 isformed) surround the interlayer insulating films 19, 23, 27 and 62 madeof low dielectric constant films.

In the structure shown in FIG. 11, a BPSG film 13 is formed on thesemiconductor substrate 11, and an SiON film 61 is formed on that BPSGfilm 13. However, this in no way restrict the present invention. Forexample, the SiON film 61 may be formed directly on the semiconductorsubstrate 11.

The low dielectric constant films 19 and 62 and the diffusion preventingfilm 18 may be replaced with a single-layer interlayer insulating film.In this case, the first wiring layer 17 is first formed, and theinterlayer insulating film is formed on both the first wiring layer 17and the SiON film 61. A second wiring layer 20 and a first via 21 of adamascene structure are formed inside the interlayer insulating film.The second wiring layer 20 is connected to the first wiring layer 17through the first via 21.

With the fourth embodiment, it is possible to obtain advantages whichare similar to those of the first embodiment.

The fourth embodiment described above can be combined with the first tothird embodiments, if so desired.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A semiconductor device comprising: a substrate; a first insulatingfilm; a first wiring layer formed in the first insulating film; a secondinsulating film formed above the first wiring layer and the firstinsulating film, the second insulating film including a low dielectricconstant film whose specific dielectric constant is not more than 3; asecond wiring layer formed in the second insulating film, wherein a partof the second wiring layer is embedded in the low dielectric constantfilm, and coupled to the first wiring layer through a first connectionsection; and a third insulating film formed above the second wiringlayer and the second insulating film and serving as one of an interlayerinsulating film and a passivation film, the third insulating filmcovering the second wiring layer, and at least one of the first andthird insulating films being one of: a film consisting essentially ofSiON, a film consisting essentially of SiN, and a laminated film beingthe films consisting essentially of SiON or SiN, respectively, whereinthe first wiring layer is physically connected to the substrate througha contact plug, and the third insulating layer is formed above adiffusion preventing film.
 2. A semiconductor device comprising: a firstinsulating film; a first wiring layer formed above the first insulatingfilm; a second insulating film formed above the first wiring layer andthe first insulating film, the second insulating film including a lowdielectric constant film whose specific dielectric constant is no morethan 3; a second wiring layer formed in the second insulating film,wherein a part of the second wiring layer is embedded in the lowdielectric constant film, and coupled to the first wiring layer througha first connection section; and a third insulating film formed above thesecond wiring layer and the second insulating film and serving as one ofan interlayer insulating film and a passivation film, the thirdinsulating film covering the second wiring layer, and at least one ofthe first and third insulating films being one of: a film consistingessentially of SiON, a film consisting essentially of SiN, and alaminated film including the films consisting essentially of SiON orSiN, respectively.
 3. A semiconductor device according to claim 1,further comprising: a fourth insulating film interposed between thesecond and third insulating films and serving as an interlayerinsulating film; and a third wiring layer formed in the fourthinsulating film and coupled to the second wiring layer through a secondconnection section, said fourth insulating film including one of a filmconsisting essentially of SiON, a film consisting essentially of SiN,and a film consisting essentially of SiO.
 4. A semiconductor deviceaccording to claim 2, further comprising: a fourth insulating filminterposed between the second and third insulating films and serving asan interlayer insulating film; and a third wiring layer formed in thefourth insulating film and coupled to the second wiring layer through asecond connection section, said fourth insulating film including one ofa film consisting essentially of SiON, a film consisting essentially ofSiN, and a film consisting essentially of SiO.
 5. A semiconductor deviceaccording to claim 1, wherein each of the film consisting essentially ofSiON, the film consisting essentially of SiN, and the laminated filmbeing the films consisting essentially of SiON or SiN respectively has athickness of not less than 100 nm.
 6. A semiconductor device accordingto claim 2, wherein each of the film consisting essentially of SiON, thefilm consisting essentially of SiN, and the laminated film being thefilms consisting essentially of SiON or SiN respectively has a thicknessof not less than 100 nm.
 7. A semiconductor device according to claim 3,wherein each of the film consisting essentially of SiON, the filmconsisting essentially of SiN, and the laminated film being the filmsconsisting essentially of SiON or SiN respectively has a thickness ofnot less than 100 nm.
 8. A semiconductor device according to claim 4,wherein each of the film consisting essentially of SiON, the filmconsisting essentially of SiN, and the laminated film being the filmsconsisting essentially of SiON or SiN respectively has a thickness ofnot less than 100 nm.
 9. A semiconductor device according to claim 1,wherein said first wiring layer is a local wiring layer.
 10. Asemiconductor device according to claim 2, wherein said first wiringlayer is a local wiring layer.
 11. A semiconductor device according toclaim 3, wherein said third wiring layer is one of a power supply lineand a grounding line.
 12. A semiconductor device according to claim 4,wherein said third wiring layer is one of a power supply line and agrounding line.
 13. A semiconductor device according to claim 1, whereinsaid first and second wiring layers and said first connection sectionform of a via-ring structure.
 14. A semiconductor device according toclaim 2, wherein said first and second wiring layers and said firstconnection section form of a via-ring structure.
 15. A semiconductordevice according to claim 13, wherein the first and second wiringlayers, which are part of the via-ring structure, are located close oradjacent to the first and third insulating films, respectively.
 16. Asemiconductor device according to claim 14, wherein the first and secondwiring layers, which are part of the via-ring structure, are locatedclose or adjacent to the first and third insulating films, respectively.17. A semiconductor device according to claim 3, wherein said first,second and third wiring layers and said first and second connectionsections form of a via-ring structure.
 18. A semiconductor deviceaccording to claim 4, wherein said first, second and third wiring layersand said first and second connection sections form of a via-ringstructure.
 19. A semiconductor device according to claim 17, wherein thefirst and third wiring layers, which are part of the via-ring structure,are located close or adjacent to the first and third insulating films,respectively.
 20. A semiconductor device according to claim 18, whereinthe first and third wiring layers, which are part of the via-ringstructure, are located close or adjacent to the first and thirdinsulating films, respectively.
 21. The semiconductor according to claim1, comprising: a fourth insulating layer formed between said first andsecond insulating layers, said fourth insulating layer including aplurality of low dielectric constant films whose specific dielectricconstant is not more than 3, said plurality of low dielectric constantfilms being respectively formed on diffusion preventing films; and aplurality of third wiring layers formed in said fourth insulating layerand connected to said first and second wiring layers, said plurality ofthird wiring layers being respectively formed in said plurality of lowdielectric constant films.
 22. The semiconductor device according toclaim 21, wherein said second and fourth insulating layers havesubstantially the same thickness.
 23. The semiconductor device accordingto claim 21, wherein: said low dielectric constant films in said secondand fourth insulating layers have substantially the same thickness; andsaid diffusion preventing films in said second and fourth insulatinglayers have substantially the same thickness.
 24. The semiconductordevice according to claim 21, wherein: said diffusion preventing filmsin said second and fourth insulating layers are formed directly on saidlow dielectric constant film in said fourth insulating layer; and saiddiffusion preventing films in said second and third insulating layersare formed directly on said low dielectric constant film in said secondinsulating layer.
 25. The semiconductor device according to claim 21,wherein: said first insulating layer comprises Si and N; and each ofsaid diffusion preventing films in said second, third and fourthinsulating layers comprises one of SiN, SiC, SiOC and SiCN.
 26. Thesemiconductor device according to claim 21, wherein: said fourthinsulating layer comprises at least two layers each containing Si and N.27. The semiconductor device according to claim 21, wherein said first,second and third wiring layers form a via-ring structure.
 28. Thesemiconductor device according to claim 27, wherein said contact plug,said first wiring layer, said second wiring layer, said third wiringlayer, said first insulating layer, and said third insulating layersurround said second insulating layer and said fourth insulating layer.29. The semiconductor device according to claim 21, wherein: an uppersurface of said second wiring layer and an upper surface of said lowdielectric constant film in said second insulating layer aresubstantially coplanar; and an upper surface of said third wiring layerand an upper surface of said low dielectric constant film in said fourthinsulating layer are substantially coplanar.
 30. The semiconductordevice according to claim 1, comprising: a connection member formed insaid third insulating layer and connected to said second wiring layer.31. The semiconductor device according to claim 1, wherein said firstand second wiring layers form a via-ring structure.
 32. Thesemiconductor device according to claim 31, wherein said first wiringlayer, said second wiring layer, said first insulating layer, and saidthird insulating layer surround said second insulating layer.
 33. Thesemiconductor device according to claim 1, comprising: an opening formedin said third insulating layer on a portion of said second wiring layer.34. The semiconductor device according to claim 33, wherein said portionof said second wiring layer serves as a pad electrode.
 35. Thesemiconductor device according to claim 1, wherein said first and thirdinsulating films include a film with low water absorption and waterpermeability.
 36. The semiconductor device according to claim 1, whereinsaid diffusion preventing film in said third insulating layer has athickness of about 70 nm.